Welcome on board

"If one does not know to which port one is sailing, no wind is favorable", Lucius Annaeus Seneca
"It is not the ship so much as the skillful sailing that assures the prosperous voyage", George William Curtis
"What can we gain by sailing to the moon if we are not able to cross the abyss that separates us from ourselves?", Thomas Merton

root@me ~ $ whoami

Some words about me


Developing innovative digital systems & design tools by following a multi-facet approach is my core belief in the last years of my work experience. A strong research background gives me the analytical framework for simplifying complexity. As a hands-on senior engineer I design efficient architectures that support real-world computing platforms. In the past years I have actively participated in several leading multi-national projects delivering world-class digital systems with highly acknowledged contribution in the realization of reconfigurable and application specific computing. Being passionate about all things to do with silicon bring-up, I am constantly looking to deploy my expertise in world-class engineering challenges. Currently, I am a Post-Doc Reasearcher at Heterogeneous Cognitive Computing Systems Group at IBM Zurich, researching novel architectures for energy-efficient FPGA accelerators, towards machine learning applications. Previsouly, I was a PhD researcher at Microlab-NTUA and a research associate at ICCS.

  • Insight - Passionate about all things to do with silicon bring-up.
  • Skills - Multi-disciplinary engineering profile & collaborative research focus.

Selected Work Samples


Take a look at my specialties.


"Skill is the unified force of experience, intellect and passion in their operation", John Ruskin
...

FPGAs

Many-accelerator Energy/Performance Efficient Architectures.
HW/SW co-Design with soft/hard IPs.
Word-length Optimization.
Real-time Debugging.
Ethernet, Wishbone, AMBA, I2C, UART IPs.
Constraints-driven Design & Verification.
Families: Xilinx Spartan, Kintex, Virtex, Altera Stratix, Arria.
...

ASICs

RTL-to-GDSII hands-on flow.
Multi-clock domain crossing.
Multi-voltage islands crossing.
Jitter-free clock-tree synthesis.
3-D chip stacking.
Low-power/Thermal-aware VLSI Design.
Formal Verification.
Static Timing Analysis with NLDM, CCS.
Libraries: Artisan TSMC 180, 130, 90, 65, 45. Faraday UMC 180, 90, FlexASIC 90, Nangate 45, SAED 90.
...

Archit/res - Design Flows

FPGA-in-the-loop Virtual Prototyping.
Hihg-Level-Synthesis C, C++, OpenCL.
Multi-processor System-on-Chip.
2-D/3-D Network-on-Chip.
Micro-architecture Exploitation.
...

EDA Tools

FPGAs: Xilinx (ISE,Vivado,Vivado HLS, Coregen, Chipscope, EDK, SDK), Altera (Quartus), Actel (Libero), Synopsys (Synplify).
ASICs: Synopsys (Design Compiler, Primetime, Formality), Cadence (IUS-Ncsim, SOC Encounter, Virtuoso)
Other/Common: Mentor (Modelsim, Catapult), Cadence OrCAD, SPICE, Simulink

Take a look at my publications


The moment a man sets his thoughts down on paper, however secretly, he is in a sense writing for publication, Raymond Chandler
Up-to-date list on dblp

On press


Some nice memories from my research journey.

Feel free to contact me


The meeting of two personalities is like the contact of two chemical substances: if there is any reaction, both are transformed, Carl Jung.
Postal address
Dionysios Diamantopoulos
Cloud FPGAs & Tape Group,
Cloud & AI Systems Research Department,
IBM Research Europe,
Säumerstrasse 4,
8803 Rüschlikon, Switzerland

Telephone
+41-44-724-85-25

Skype id
dionisis.diamantopoulos

E-mail
dionisios.diamantopoulos@TYPICAL_GMAIL_COM_SUFFIX