Developing innovative digital systems & design tools by following a multi-facet approach is my core belief in the last years of my work experience. A strong research background gives me the analytical framework for simplifying complexity. As a hands-on senior engineer I design efficient architectures that support real-world computing platforms. In the past years I have actively participated in several leading multi-national projects delivering world-class digital systems with highly acknowledged contribution in the realization of reconfigurable and application specific computing. Being passionate about all things to do with silicon bring-up, I am constantly looking to deploy my expertise in world-class engineering challenges. Currently, I am a Post-Doc Reasearcher at Heterogeneous Cognitive Computing Systems Group at IBM Zurich, researching novel architectures for energy-efficient FPGA accelerators, towards machine learning applications. Previsouly, I was a PhD researcher at Microlab-NTUA and a research associate at ICCS.
Principal Investigator
Speeding-up computer vision algorithms (up to 1.111x) with customized FPGA accelerators, for autonomous space rover navigation.
PhD Researcher
Accelerating image feature extraction on a car's ECU, targeting automotive industry. A novel virtualization framewrok supports the early design prototyping.
PhD Researcher
Extending High Level Synthesis tools with Dynamic Memory Management, on Many-Accelerator systems. The novel technique delivers gains in FPGA's accelerators density (3.8x) and throughput (21.4x).
Senior Digital DSP Designer
Developing and implementing onto FPGA, VHDL IP cores of baseband OFDM transceiver, targeting 1Gbps wireless link on LTE/WiMAX backbone networks.
PhD Researcher
Framework for performing rapid evaluation of three-dimensional (3D) chip stacking SoCs. Experimentation with DSP kernels showed average power savings of 20% on a 2-tiers Leon3 processor.
PhD Researcher
Developing a genetic algorithm-based FPGA placer. The novel placer exhibits inherent parallelism and achieves average reduction of execution run-time and application's delay by 67x and 16%, respectively.
PhD Researcher
Experimenting with irregular Network-on-Chip topologies. The proposed heterogeneous 3-D routers lead to 25% higher maximum operation frequency and 39% lower power consumption, as compared to the uniform 3-D NoCs.
PhD Researcher
Thermal-aware exploration at the micro-architecture level for temperature hotspots elimination. The novel design tool leads to temperature reduction of 17 Kelvin degrees and aging phenomena improvement up to 14%.
Many thanks @ Cadence Design Systems, Inc. for the prize of Automotive Embedded System contest. CDNLive EMEA 2013 was not only an outstanding event but also a great opportunity for Cadence to attribute add-on value for every word of the motto "connect-share-inspire", justifying why is the No1 EDA company worldwide. Also many thanks to Dr. Kostas Siozios, Prof. George Economakos and Prof. Dimitrios Soudris for their guidance and support throughout this project.
Greece: the gods of technology. Since 2011 Greece tries to organize its industry in "clusters". After the information technology sector, today is the aerospace industry, which is trying to win contracts from the European Space Agency but also among Americans, Israelis and Chinese. The story in Athens from Adéa Guillot.
HiPEAC student Dionysios Diamantopoulos from NTU Athens visits Cadence’s office in Munich as a finalist of their sponsored thesis contest for automotive embedded systems. Report in HiPEACinfo 33, pages 18-19.
A complete hands-on tutorial on Robotic Operating System (ROS). Only in Greek. Report in Linux Inside, Issue 8, pages 68-69.
A cover story for projects SPARTAN-SEXTANT funded from ESA. Only in Greek. Report in Epikaira, Issue 116, pages 102-103.
An article covering aspects of the projects SPARTAN-SEXTANT funded from ESA. Only in Greek. Report in Eleytheros Typos, Issue Monday 1 October 2012, page 51.
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